PCIe Interrupts from Qsys/Arria II GX

MSI-X interrupts are (effectively) edge sensitive.

So on the leading edge of the internal IRQ line you must generate the correct PCIe master cycle (by a write through the cra) to raise the interrupt.

The host ISR will then need to access the device in order to drop the IRQ line (and then maybe check memory for any actions).

For our systems I've written a simple bit of logic that implements the MSI-X-table and pending bit array and writes the high address bits to one of the address mapping tables just before doing the write that raises the interrupt itself. Not difficult and I'm a software engineer.