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ASvir2's avatar
ASvir2
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7 years ago

PCIE HIP msi_request occurring before the corresponding avalon stream

Hi everyone, I'm using pcie hip in a multifunction design (I have 2 functions). Due to difference in propagation delay of the Avalon stream TLPs and the msi interrupt requests in the app layer of...
Nathan_R_Intel's avatar
Nathan_R_Intel
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7 years ago

Hie,

Could you help clarify your question a little more. Are you saying the write TLP is ~20 clock cycles after app_msi_req? This could be dependent on when app_msi_tc and app_msi_num has a valid window.

Hence, this might not be entirely dependent on the PCie HIP.

The following wiki side has some timing diagram related to app_msi_req.

https://fpgawiki.intel.com/wiki/Handling_PCIe_Interrupts

Regards,

Nathan