Altera_Forum
Honored Contributor
12 years agoPCIe HIP and Credits
I am using a SIV with the PCIe HIP. I have a functional application layer using DMA and things are running well. So why am I writing?
Recently, I re-wrote much of the TX path to increase bandwidth. During my iterations, I temporarily removed the credit checking mechanism I wrote and ran some tests with SignalTap. Based on my observations, I saw credits being consumed (only P_DATA). I was concerned that the core might lockup when credits ran out, but I noticed that the core would de-assert tx_ready when credits got low. To my surprise, I could DMA data ~3GBps (Gen2 x8) with credits consistently running out and throttling being handled by the ready flag from the core. Does this mean that manual credit checking is unnecessary, as the core will handle cases when the credits go too low? Seems unlikely. Have others observed this? What approaches to credit checking have you implemented? Thanks for the advice! Jay