Forum Discussion
PCIe HIP - only one legacy INTX interrupt available
- 4 years ago
Hi,
Apologize for late, hope this helpful.
There is two AVMM example available in the Quartus, one is AVMM another one is AVMM+- For the AVMM example design indeed you will get "1"
The document provided by you early 3.2.3.3.1. Interrupt Signals Available when the PCIe Hard IP is an... (intel.com)
Shows that the 4bits intx_req_i is only available for AVMM+
I try to run the example design (AVMM+) and I get the result below
Let me know if this is helpful, please correct me if i am wrong.
Regards,
Wincent_C
Hi,
Do you clear the Interrupt Disable bit, which is bit 10 of the Command register?
Also, please ensure that you had turned off the MSI Enable bit.
Let me know if the problem still happen after that.
Regards,
Wincent_Intel
- jmcguire34 years ago
Occasional Contributor
Apparently I wasn't clear - allow me to clarify. This isn't a run-time configuration issue, it's a compile-time resource allocation. The CRA is not enabled in the Platform Designer tool (see attached.) The "CRA Avalon-MM slave port" box is un-checked, so there is no interface with which to set or clear bits in the PCIe IP register set. The "Export MSI/MSI-X interfaces" box is checked, as this is necessary to expose the INTx legacy interrupt conduit to the Platform Designer interconnect area.
Only one INTx interrupt shows up. In isolation it works fine. I need to add another legacy peripheral that expects to use the hardware-driven INTA/INTB/INTC/INTD legacy interrupts held over from the olden PCI days - from back when PCI cards had access to only the four INTx hardware interrupts and MSI hadn't been invented yet. The Platform Designer tool refuses to allow me to change the width of the INTx interface to anything other than "1". The documentation referenced upthread indicates that it can have a width of 4, corresponding to the legacy PCI INTA/B/C/D structure.