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Occasional ContributorPCIe HIP - only one legacy INTX interrupt available
Hi,
Apologize for late, hope this helpful.
There is two AVMM example available in the Quartus, one is AVMM another one is AVMM+- For the AVMM example design indeed you will get "1"
The document provided by you early 3.2.3.3.1. Interrupt Signals Available when the PCIe Hard IP is an... (intel.com)
Shows that the 4bits intx_req_i is only available for AVMM+
I try to run the example design (AVMM+) and I get the result below
Let me know if this is helpful, please correct me if i am wrong.
Regards,
Wincent_C
Regular ContributorHi,
Thanks for reaching, May I know which device and user guide you are referring?
PCIe endpoint supports both legacy interrupts and MSI interrupts.
However, MSI and legacy interrupts are mutually exclusive, it means only 1 type of interrupt can be enabled at a time.
To switch interrupt mode during operation, software must first enable the new mode and then disable the previous mode.
To enable legacy interrupts when the current interrupt mode is MSI, software must first turn off the Disable Interrupt
bit (bit[10] of the Command register at configuration space offset 0x4) and then turn off the MSI Enable bit.
1. Off the Interrupt Disable bit[10] of Command register at configuration space offset register 0x4 to enable legacy interrupt.
2. Off the MSI Enable of MSI Control register, this bit is mapped to bit[16] of offset 0x50 in configuration space register.
3. Set the bit[1] Memory Space and Bus Master bit[2] of Command Register at configuration space offset register 0x4 to enable the ability to generate/send MSI message.
Once app_int_sts is asserted by its source, the PCIe core will sends out an Assert_INTA message TLP to root port.
Below link also has information about legacy interrupt, help it helps.
https://community.intel.com/t5/FPGA-Wiki/Handling-PCIe-Interrupts/ta-p/736044
Regards
Wincent_Intel
Occasional ContributorThis is a legacy interrupt availability issue ... has nothing to do with MSI. In fact, I have no resources available to configure MSI registers on the target platform, and the legacy interrupt operates properly with a single device attached.
Problem exists for both a Cyclone 10 GX and Stratix 10 MX target device - the latter having an H-tile PCIe HardIP core, whereas the former has the HardIP integrated onto the FPGA die. The Cyclone documentation suggests support for multiple INTx interrupts, but the H-tile document comes right out and says so -
3.2.3.3.1. Interrupt Signals Available when the PCIe Hard IP is an... (intel.com)
However, I am unable to configure the Hard IP through Platform Designer to allow access to more than one legacy INTx interrupt. When the pull-down menu is changed to "standard logic vector," the width field remains gray and is fixed to "1". (screenshot is attached)
