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Altera_Forum
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10 years ago

PCIe Force Gen1 Link

I've built a design around a Stratix V and the Avalon-ST Hard IP Core. The device is designed for Gen3x8 which is working fine. I now want to connect the design to a laptop via a Gen1x1 Express...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

That's what I would assume, except it fails to enumerate correctly on this particular laptop with the Gen3x8 configuration, but does enumerate with a Gen1x1 core (though the clock frequency and data width changes of the core mean that I will have to do a lot more testing to get my application layer for that one working). It's possible I suppose that it is an issue with the fact that there are 8 lanes, of which 4 aren't connected on the OSS board (they will be floating inputs) and 3 aren't used.

I see that there is a Hard IP Reconfiguration Interface which looks like it should be possible to reconfigure the compiled core. But there is no register listing saying what can be changed.