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MateuszZ's avatar
MateuszZ
Icon for New Contributor rankNew Contributor
2 years ago
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PCIe DMA write posted or non-posted

Hello, i have question about intel PCIe driver for (in this case) Cyclone 10 devices. When using DMA, FPGA becomes master of operations. After completing its job, it sends interrupt with MSI me...
Pcie
  • Harshx's avatar
    Harshx
    2 years ago

    What type of messages FPGA uses when it tries to write data to processor?

    Posted Write Transactions.

    Ref: 3. Intel® Arria® 10 or Intel® Cyclone® 10 GX Parameter Settings


    When we send MSI interrupt? After completing posted write transfer or after getting confirmation about completion of non-posted transfer?

    Posted write case: No acknowledgement -> MSI is not directly tied to the completion -> no completion needed

    Non Posted case: acknowledgement TLP -> Once TLP received initiator can send an MSI interrupt

    Conclusion: MSI are sent after the completion.


Harshx's avatar
Harshx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Second question - if i get crc error with posted message, will driver corrupt my data in device memory? (just to confirm )

No (Transmission error-> crc error is detected -> corrupted TLP packet is discarded -> No data is written to the memory.)

Is there any difference when using other device families (+ Agilex 5)?

Yes, Agilex 5 supports link speed upto 4.0 (cyclone 10 upto 2.0 only) different FPGAs have different Capabilities and varies in terms of performance, speed, number of transceivers availability [Vary with Tiles (F-tile, P-tile, H-tile, R-tile,etc)]

Check: PCIe* Intel® FPGA IP