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EastGun-A's avatar
EastGun-A
Icon for New Contributor rankNew Contributor
3 years ago
Solved

pcie DMA memory read & write TLP

Hello, while studying the pcie protocol, I was confused about DMA and PIO, so I asked a question. Thank you so much for always responding kindly. PIO seems to work like the existing pcie spec, but D...
Pcie
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi


    In the context of PCIe (Peripheral Component Interconnect Express), a Memory Write (MWr) Transaction Layer Packet (TLP) is used to transfer data from the initiator (the device initiating the transaction) to the target (the device receiving the transaction).

    During a Memory Write transaction, the data is indeed used in the DMA (Direct Memory Access) process. DMA allows devices to transfer data directly to and from system memory without involving the CPU. The data sent in the MWr TLP is typically stored in a specific memory location or register within the target device.

    So, the data carried by the MWr TLP is not unnecessary. It serves the purpose of updating or modifying data in the target device's memory or registers, and DMA facilitates this data transfer without CPU intervention.


    Regards,

    Wincent_Intel


Rajat_Dongre_79's avatar
Rajat_Dongre_79
Icon for New Contributor rankNew Contributor
2 years ago
  1. I am getting page fault while accessing another PCI NTB switch config space.
  1. The steps that I followed are below:
  1. I am using two PCIe NTB switch.
  • Microchip pcie ntb switch
  • Microchip Pcie ntb switch

Structure:

2.both switch is having two partition one is upstream and NT and second is NT only and cross link between both switch.

  1. I have added translated base address to 0x4000000 to BAR2 LUT table at index 0. and added this address in another switch partition 1 BAR 0 (translated base address)
  1. In switch 1: I have added base address to LUT table at 0th Index Translated Base address : 0x04000000 Destinition partion : 1
  1. I am trying to fetch address of it to access config space of another switch (SW2 NTB1 BAR0) so the address for this is BAR2 + LUT0.
  1. BAR2's physical address is 0xaf310004
  1. To access LUT0 entry. = BAR2 + LUT0 = af310004
  1. but when i am trying access Device ID of another PCIe switch it is giving page fault.
  1. please let me know where I am wrong

10 I checked physical crosslink using its chiplink tool In switch 2 I have added BAR0 base address to 0x4000000 using static enumeration.

Your help is really appreatiated

`/*short code */

PHYS_ADDR *sw2Ntb1regAddr;

UINT32 sizeMapReg;

UINT32 data;

idt_ntb_peer_mw_set_trans(ndev, 0, 0, 0x04000000, 0);

/* lukup table idx 0 */

ret = idt_ntb_peer_mw_get_addr(ndev, 0, &sw2Ntb1regAddr, &sizeMapReg);

if(ret != Success)

{

console_printf("NP: %s @ line %d, ret = %d\n", __FUNCTION__, __LINE__, ret);

}

/* Trying to access Device ID : register address : 0x2000 from SW2 PCIe NTB config space * /

/*sw2NtbregAddr = 0xaf310004*/

memcpy(&data, sw2NtbregAddr + 0x2000, 4); /* page fault error */

printf("Device ID %X", data); `