Forum Discussion
New Contributorpcie DMA memory read & write TLP
Hi
In the context of PCIe (Peripheral Component Interconnect Express), a Memory Write (MWr) Transaction Layer Packet (TLP) is used to transfer data from the initiator (the device initiating the transaction) to the target (the device receiving the transaction).
During a Memory Write transaction, the data is indeed used in the DMA (Direct Memory Access) process. DMA allows devices to transfer data directly to and from system memory without involving the CPU. The data sent in the MWr TLP is typically stored in a specific memory location or register within the target device.
So, the data carried by the MWr TLP is not unnecessary. It serves the purpose of updating or modifying data in the target device's memory or registers, and DMA facilitates this data transfer without CPU intervention.
Regards,
Wincent_Intel
Regular ContributorHi,
In PCIe, DMA (Direct Memory Access) and PIO (Programmed Input/Output) are two different methods used for data transfer between devices. Let's clarify how they work and their relationship with PCIe TLPs (Transaction Layer Packets).
- DMA (Direct Memory Access):
- When using DMA, the host device initiates the data transfer by sending a PCIe Memory Read Request TLP to the endpoint (EP). This request includes the address in the host memory from where the data should be read. The DMA engine in the EP receives this request and performs a memory read operation to fetch the data from the host memory. Once the data is read, the DMA engine can store it locally in the EP or perform other processing tasks.
When the host wants to receive data from the EP through DMA, it sends a PCIe Memory Write Request TLP to the EP, specifying the address in host memory where the EP should write the data. The EP's DMA engine reads the data from its local memory and writes it to the specified address in the host memory.
The completion of the DMA transfer is typically handled using PCIe Completion TLPs. When the EP completes the requested operation (read or write), it generates a Completion TLP to indicate the status and transfer the completion data (if applicable) back to the host. The Completion TLP contains the necessary information for the host to identify the completion and retrieve the transferred data, if any.
- PIO (Programmed Input/Output):
- PIO, on the other hand, involves the host or EP directly reading or writing data to/from the PCIe configuration or I/O space registers of the target device. This method is typically used for control and configuration purposes rather than large data transfers. PIO operations are not explicitly associated with PCIe Memory Read or Write Request TLPs.
Regarding your specific question about the relationship between PCIe TLPs and DMA engine, the TLPs (such as Memory Read/Write Request TLPs and Completion TLPs) are used to initiate and acknowledge the DMA operations. They carry the necessary information for the host and EP to coordinate and perform the data transfer. The DMA engine in the EP is responsible for processing the TLPs and performing the actual data movements between the host memory and local EP memory.
Please note that the exact implementation details of DMA and PIO can vary depending on the specific PCIe device and its configuration, but this general explanation should help you understand the concept behind these mechanisms.
Let me know if further clarification is needed.
Regards,
Wincent_Intel
New ContributorThank you very much for your reply.
1. It is said that the Memory Read TLP (Fmt+ type = 0010000) sends a request pointing to the host memory address through the PCI express link from the host to the DMA. Doesn't the address field of the Memory Rd TLP point to the address of the destination (EP)? (PCI express 4.0 spec, P-tile)
I am confused whether the form of the packet transmitted to the DMA EP through the PCI express link is different
2. Then, I understand that it is specified in the form shown in the figure. Does the request to the host memory also have the same TLP form and the address of the host memory represents the address field of Memory Rd?
Is there a separate address? (Does the host memory also have an independent EP?)
3. In the case of the Mwr in the figure, is the DMA EP receiving the Memory Write TLP, reinterpreting it, generating the Memory Write TLP again from the DMA to the host memory address, and sending it?
Sorry for the difficult question
The TLP that meets the Pcie 4.0 spec is transmitted through the PCI express link, but I ask a question because I do not understand how DMA works according to the TLP.
In addition, if you do a PIO test and look at the dumping signal with a Stratix 10 FPGA, it seems to be proceeding with MWR and MRD while following the Pcie 4.0 spec. I wonder what it means that TLP and PIO are not explicitly associated.
