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EastGun-A's avatar
EastGun-A
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3 years ago
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pcie DMA memory read & write TLP

Hello, while studying the pcie protocol, I was confused about DMA and PIO, so I asked a question. Thank you so much for always responding kindly. PIO seems to work like the existing pcie spec, but D...
Pcie
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi


    In the context of PCIe (Peripheral Component Interconnect Express), a Memory Write (MWr) Transaction Layer Packet (TLP) is used to transfer data from the initiator (the device initiating the transaction) to the target (the device receiving the transaction).

    During a Memory Write transaction, the data is indeed used in the DMA (Direct Memory Access) process. DMA allows devices to transfer data directly to and from system memory without involving the CPU. The data sent in the MWr TLP is typically stored in a specific memory location or register within the target device.

    So, the data carried by the MWr TLP is not unnecessary. It serves the purpose of updating or modifying data in the target device's memory or registers, and DMA facilitates this data transfer without CPU intervention.


    Regards,

    Wincent_Intel


EastGun-A's avatar
EastGun-A
Icon for New Contributor rankNew Contributor
3 years ago

Thank you very much for your reply.

1. It is said that the Memory Read TLP (Fmt+ type = 0010000) sends a request pointing to the host memory address through the PCI express link from the host to the DMA. Doesn't the address field of the Memory Rd TLP point to the address of the destination (EP)? (PCI express 4.0 spec, P-tile)

I am confused whether the form of the packet transmitted to the DMA EP through the PCI express link is different

2. Then, I understand that it is specified in the form shown in the figure. Does the request to the host memory also have the same TLP form and the address of the host memory represents the address field of Memory Rd?
Is there a separate address? (Does the host memory also have an independent EP?)

3. In the case of the Mwr in the figure, is the DMA EP receiving the Memory Write TLP, reinterpreting it, generating the Memory Write TLP again from the DMA to the host memory address, and sending it?

Sorry for the difficult question

The TLP that meets the Pcie 4.0 spec is transmitted through the PCI express link, but I ask a question because I do not understand how DMA works according to the TLP.

In addition, if you do a PIO test and look at the dumping signal with a Stratix 10 FPGA, it seems to be proceeding with MWR and MRD while following the Pcie 4.0 spec. I wonder what it means that TLP and PIO are not explicitly associated.