pci express sopc vs qsys

hey dave..

thanks, but i think that the bar has got an avalon address, as u can see in the picture of my first post. the message section of qsys says: bar0, avalon base address start: .....

i think i know how addresses are mapped let´s say inside the fpga between avalon masters and avalon slaves. but my idea was that there must be also an address mapping between the pci express and my os on the host pc. when i want to serve i/o s from that os i don´t know which base address (or offset address) i have to write to from outside the fpga to reach the appropriate i/o. :confused:

actually it was quite obvious in sopc....

cheers,