Honored Contributor
Honored ContributorHi,
I have two question, I'm working on the basic SOPC builder Design example ( chapter 8 in the PCIe complier User guide). I'm using Arria GX kit dev - simulation running fine, while I was synthesis the design I got a critical warning of crossing between clocks if one of the clocks are from transceiver - and the constrains at the pcie_complier.sdc file are ignored - I try to use set false path between those clocks -no critical warning. I use simple Linux application that write and read packet to/from host to local RAM, low rate of packet everything work fine. I moved to higher rate (not real high 34MByte/s) and after 10,000 packets the DMA "stuck" und don't send back the Interrupt, I add signal tap on the Avalon and on the 512 test signal, and when this occur the error signal are asserted on error sequence number at the Data link layer, my question are : 1. Constrains- what should I do with this crossing clock critical warning if not ignore it? 2. Avalon MM seems to be problematic in case of error from the transaction layer (PCIe) -no signal that indicate error on this transaction? Thank you, Tal.
