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Matt_Caves
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6 years ago
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PCI Express High Performance Reference Design AN-456 on Cyclone IV - Hangs PC on boot?

I've been trying to get the PCIe High Performance Reference Design going from AN-456, but it doesn't seem to work, it just hangs the PC at the BIOS at boot.

I'm using a Cyclone IV GX (EP4CGX15BF14C6) dev board from devboards.de.

The reference design is for a larger chip, so I go in and change that, assign all the pins to the correct locations. I'm also using a 25MHz 'free_clk' instead of the 100MHz that it's designed for, so I reconfigure the PLL to give the correct 50MHz and 125MHz outputs.

It seems to compile OK, I program the board, restart the PC and it just hangs at the BIOS, nothing comes up on the screen. The 'alive_led' is flashing at around 3 flashes/second, which I think is correct.

Any ideas on why this design won't work? I've seen another post I think talking about similar issues. but there was no resolution :(

Thanks,

Matt

  • Matt_Caves's avatar
    Matt_Caves
    6 years ago

    Hi,

    Thanks for your reply. Yes, your understanding is correct.

    OK we have just found the issue! 😀

    The problem was caused by the BAR 0 register being 256MB in size. Apparently some BIOS don't like the fact that it's so large. We were trying this on an older Dell PC, which didn't like it. When we reduced the size of the BAR 0 register down to 64kB it worked fine. After this we tried the original 256MB in another newer PC and it worked fine.

    Thank you for your advice to look at the LTSSM register on the Signaltap, we did look at that and saw that it was reaching state L0, which then led us to find the BAR 0 memory size problem.

    Cheers,

    Matt

2 Replies

  • Matt_Caves's avatar
    Matt_Caves
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    Thanks for your reply. Yes, your understanding is correct.

    OK we have just found the issue! 😀

    The problem was caused by the BAR 0 register being 256MB in size. Apparently some BIOS don't like the fact that it's so large. We were trying this on an older Dell PC, which didn't like it. When we reduced the size of the BAR 0 register down to 64kB it worked fine. After this we tried the original 256MB in another newer PC and it worked fine.

    Thank you for your advice to look at the LTSSM register on the Signaltap, we did look at that and saw that it was reaching state L0, which then led us to find the BAR 0 memory size problem.

    Cheers,

    Matt

  • BoonT_Intel's avatar
    BoonT_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hi Sir,

    My understanding is the design is originally create for Intel FPGA CIV GX dev kit. But you migrate the design to third party board with other variant and change some of the ref clock frequency due to the board capability.

    I am sorry to said that I am unable to read the third party board website due to other language. But may I know that do you have chance to test on the third party PCIe reference design and confirm the IP is work with the board?

    Also, my second suggestion is to open the signaltap (hip_c4gx_gen1_x4.stp) of the reference design and check the LTSSM status and other signal see where the abnormal occur.