Hi everybody,
I`m new on this forum and in the usage of Altera product, then be patients please. In 2 days of research, I`m not able to find the answer to my questions. I want read and write from my FPGA (Stratix V) to the Host PC RAM, using PCIe bus, without involve the CPU (like mulligan252). In the specific, FPGA writes in RAM and when the data transfer is finished, FPGA sends an interrupt to the CPU. When CPU receives the interrupt from the FPGA, reads data from PC RAM. In this thread is described how the FPGA side can be realized. My questions are:
how can I realize the PC communication side?
Is there some driver, API or library to do that? where can I find them?
Thanks you very much
Federico