PCI Burst Read Transaction, Not Avalable, Please Help!

I used PCI IP Core(Pci_compiler and Master&Target Mode, Default Option) and testbanch source(modify) in pci_compiler manual

But don't pci master burst read transaction.(PCI Master burst Write Transaction is vary well transaction)

I do some signal check!

1) request signal -- ok!

2) grant signal -- ok!(my target(pci master) Address and C/BE# load -- ok)

3) Initiator Ready signal(IRDY) -- ok!

4) Target Ready signal(TRDY) -- fail! <-- I don't understand, Why don't pc(target) Ready

please help me,, Why Target(PC) TRDY Signal don't assert