Altera_Forum
Honored Contributor
9 years agoPC doesn't boot when RXM_BAR4 connects ext DDR3 cntrlr in AVMM DMA PCIe Qsys design
Hi,
I am stumped with this one. I have modified the Altera stratix V PCIe AVMM DMA reference design to include a UniPhy based external DDR3 controller to the Qsys. The target fpga is sitting on a PCIe development board. It is a PCIe x4 gen 3. No CvP. The qsys has both external memory controller and on-chip memory of 64KB. I have verified that the address regions do not overlap between the external memory and on-chip memory. A couple of stumbling blocks that I cannot explain - 1. When I connect RXM_Bar4 to the DDR3 controller's AVL interface, the PC doesn't boot. With signaltap I see that the DDR3 controller has calibrated. If remove the RXM_Bar4 connection to the DDR3 controller. The PC boots and I can access the DDR3 while maintaining data integrity. So what gives? 2. If I remove the RXM_Bar4 connection to the DDR3 controller, then the BAR4's address region is automatically adjusted down from 4GB (32bits) to 64KB(16bits). Thank you in advance for helping me figure this out. Best regards, Sanjay