P-tile PCIe what if is rx_st_ready_i deasserted?

Thank you for your answer, however I do not find the answer clear.

All the points you mention are in the documentation, and I have read the documentation.

However, the last sentence you suggest you are summarizing the documentation "In short, ..." but you are coming up with a new fact: the hard IP will stop transferring TLP packets back to host.

So you are suggesting when I disable the inbound direction (Root Complex to FPGA) the Hard IP will stop transferring TLPs upstream (towards Root Complex) also? This is not documented.

What happens to the inbound traffic (Root Complex to FPGA) when I deassert rx_st_ready_i? Will these TLPs be dropped inside the Hard IP?