overflow in clocked video input (HD-SDI as input)

I spend several days observing the signal waveform in my design by using SignalTapII.

The SGDMA ready signal (which is one of avalon-st signal) becomes low after the first two lines.

Then, the overflow in CVI happens.

So I suspect whether SGDMA (st-to-mm) has written to DDR3 correctly and check the input and output signals of SGDMA.

For the pixels in the first two lines, I can see their corresponding data in the writedata signals of avalon-mm interface to DDR3 controller.

The pixels of the rest lines are not seen in the avalon-st interface due to the low ready signal and backpressure.

So I think the write operation should work fine.

Now I really don't know what makes SGDMA deassert the ready signal and causes CVI overflow.

Could anyone please give me some ideas?

Thanks.