colinz
New Contributor
2 years agooneAPI MVDR Beamforming Sample
This sample uses IO Pipes and UDP. If I want to run this sample in an Agilex FPGA card, does that mean the FPGA need to have Ethernet and TCP/IP ip core?
Thanks.
Hi @colinz,
Thank you for posting in Intel community forum and hope all is well.
Based on the document would assump that you are running the fill system compilation, and for that the BSP that you would be included would have the required IP added accordingly.
Please let me know if I misunderstood the situation.
Best Wishes
BB