Onchip RAM Corrupted by Reset

The RAM corruption changes the reset vector content (just to re-confirm)?

Are you using Nios II/f core? Maybe you can enable the ECC feature.

Does the PCIE sends interrupt to Nios?

You stated that the DDR memory supplies clock (afi_clk) to the Nios and user system (including the RAM), do you also use the afi_reset supplied? Just to ensure that afi_clk is stable and locked and that Nios and the user system can run properly. From your first post, the soft reset from PCIE is connected to the DDR controller and user system and that the user system will be up and running once the PCIE core is ready but your DDR memory is the one supplying the clock to user system?

One thing that can you can do is to remove the DDR3 controller, leaving just the PCIe and Nios/RAM, and perform the restart PC sequence. We could rule out anything that is related to DDR3. We could use crystal oscillator clock (on-board clock) to run Nios/RAM.

I also assume that your design is meeting timing.

I have heard of RAM corruption with asynchronous reset but the probability of occurring is like 1/500 resets. But you are getting it every time you restart, which is a 100% chance hit rate (You must have been in or out of luck).