Hi Nathan,
Thanks for the response.
I get what your saying, but I feel your answer is a bit short sighted.
First that the NVME driver is at fault because it reports an error. This is the NVME driver in the mainline Linux kernel, it is used by many different devices. So I don't expect a bug in that part of the kernel.
Second, the NVME driver is actually from Intel, it is in the 3rd line of the core.c driver source. I know that Intel is big and it is form a completely different division. But a comment like this feels dismissive "Not our bug".
Sorry for these comments, but that bugged me a bit today.
Back to a constructive discussion:
I am pretty sure the problem is in either our HDL / Qsys design or the configuration of the kernel through the device tree.
Below is a the PCIe part of the device tree.
We have the PCIe Txs port connected to the high performance master of the HPS at offset 0x10000000
The PCIe Cra is connected to the low performance port at offset 0x0
The MSI interrupt controller is connected to the low performance port at offset 0x4080 and 0x4000
Attached is the archive of our project that we use now and it only contains the HPS and the PCIe core.
I hope you can help me figure out where we made our mistake.
Kind regards,
Rienk
pcie_0_pcie_a10_hip_avmm: pcie@0xd0000000 {
status = "okay";
compatible = "altr,pcie-root-port-16.1", "altr,pcie-root-port-1.0";
reg = <0xd0000000 0x10000000>,
<0xff210000 0x00004000>;
reg-names = "Txs", "Cra";
interrupt-parent = <&hps_arm_gic_0>;
interrupts = <0 25 4>; // irq6
interrupt-controller;
#interrupt-cells = <1>;
device_type = "pci"; /* embeddedsw.dts.params.device_type type STRING */
bus-range = <0x00000000 0x000000ff>;
ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
msi-parent = <&pcie_0_msi_to_gic_gen_0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_0_pcie_a10_hip_avmm 1>,
<0 0 0 2 &pcie_0_pcie_a10_hip_avmm 2>,
<0 0 0 3 &pcie_0_pcie_a10_hip_avmm 3>,
<0 0 0 4 &pcie_0_pcie_a10_hip_avmm 4>;
}; //end pcie@0x010000000 (pcie_0_pcie_a10_hip_avmm)
pcie_0_msi_to_gic_gen_0: msi@0xff214080 {
status = "okay";
compatible = "altr,msi-1.0", "altr,msi-1.0";
reg = <0xff214080 0x00000010>,
<0xff214000 0x00000080>;
reg-names = "csr", "vector_slave";
num-vectors = <32>; /* embeddedsw.dts.params.num-vectors type NUMBER */
interrupt-parent = <&hps_arm_gic_0>;
interrupts = <0 24 4>; // irq5
clocks = <&h2f_lw_clk>;
msi-controller = <1>; /* embeddedsw.dts.params.msi-controller type NUMBER */
}; //end msi@0x100014080 (pcie_0_msi_to_gic_gen_0)
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