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Altera_Forum
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10 years ago

Not able to generate HDL because of tight clock constraints -Altera DSP builder

Hi, My name is Wasim. I am using Altera DSP builder for designing a system for Altera Stratix IV FPGA. I am able to simulate the system in simulink but when I generate the hardware it s...
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Altera_Forum
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10 years ago

Can we see a screenshot of your design? This is usually caused by you having a loop without enough delay around it to meet your desired clock speed.