Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorNot able to generate HDL because of tight clock constraints -Altera DSP builder
Hi, My name is Wasim. I am using Altera DSP builder for designing a system for Altera Stratix IV FPGA. I am able to simulate the system in simulink but when I generate the hardware it s...
Altera_ForumHonored Contributor
Honored ContributorCan we see a screenshot of your design? This is usually caused by you having a loop without enough delay around it to meet your desired clock speed.
