Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Nios II interfering with VGA Data

Hi! I'm trying to implement a Nios II core to manage an RS232 link on a Cyclone IV embedded in a DE2-115 board. On the same FPGA, but unrelated to the Nios II, is a VGA controller writing data...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Actually I was thinking more along the lines of the off-chip timing between your VGA IP and the DAC. I would find the datasheet for the DAC and make sure you constrain that interface accordingly otherwise I would assuming random bits would be corrupt depending on the fitting results of your design.

I'm not too bummed about the Habs this year, they get draft picks, hopefully some good management, Toronto missed again, ...... and if I'm lucky the Bruins will golfing soon too :)