Forum Discussion
Altera_Forum
Honored Contributor
14 years agoNios II interfering with VGA Data
Hi! I'm trying to implement a Nios II core to manage an RS232 link on a Cyclone IV embedded in a DE2-115 board. On the same FPGA, but unrelated to the Nios II, is a VGA controller writing data...
Altera_Forum
Honored Contributor
14 years agoThere's clearly a functioning image; for some reason, however, there seem to be bands of semi-regular corruptions popping up in the final image. There are two main regions of corruptions that happen at regular spaced intervals (appears to be about every ten-fifteen pixels or so). As to the timing concerns, TimeQuest yielded an Fmax of 153 MHz- two to three times what I'm running at. I'll give your other suggestions a shot. Thanks for your help!
Sorry to see the Habs didn't make it, by the way. Next year!