New IP development

Hello all,

After giving it several thoughts, I have decided on to have some sort of implementation like this:

BIGNUM IP core:

With a 1024 bit Avalon master interface with on-chip memory to read the operands into the operand registers as suggested by Ted.

With a 32 bit Avalon master interface with NIOS ii to decide on the address from which we can read the operands.

The 1024 bit on-chip memory interface will copy the value from memory onto the registers only if valid addresses are read using this 32 bit interface first

and the values will be read from those valid addresses. This 32-bit interface also gives the 'opcode' interface for an operation to perform, as requested by the NIOSII.

Like if the data read is 0, it corresponds to BIGNUMADD, if the data read is 1, it corresponds to BIGNUMSUB etc.

So I will add a user note saying please exclude the 'opcode' values from being used as the operand read addresses.

I did not see any edge of using a custom instruction with the IP core for the below reasons:

1) If the IP core has to get values from the custom instruction, then the NIOS II should talk with the custom instruction first, then the custom instr. send the output to the

NIOS II and then the NIOS II has to give those values to the IP core.

2) I did not see any such custom instruction interface in the Avalon Interface spec. (I saw clock, reset, interrupt, MM, ST, tristate etc)

3) The custom instruction does not do anything specific in this scenario, O/P = I/P. So we can avoid an overhead.

Instead, I plan to use another 32 bit MM master interface in the IP core as described above.

Please correct me if I miss something here. I really appreciate everyone's patience.

Thank You,

Akhil