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Altera_Forum
Honored Contributor
12 years agoI seem to have the same problem. I'm using Quartus 13.0sp1, TSE 13.0 10/100M Small MAC on a Cyclone IV E connected to a Micrel KSZ8021RNL with a small custom wrapper to convert RMII to MII. The PHY works fine, I can configure it using a custom MIIM design and I see data coming in through the RMII and MII interface when connected to an Ethernet network.
However, the waitrequest signal of the MM interface stays high as described by the OP. My clocks are 100Mhz on clk, ff_rx_clk, ff_tx_clk, and a locally generated (just divide by 4 in logic, derived from the 100Mhz clk) 25Mhz for rx_clk and tx_clk. Those clocks are all active according to signaltab. I have not yet connected any logic to the FIFO interfaces except the clocks, but I DID set the "noprune" attribute on all the ff_rx_* signals to keep them visible in signaltab (and it seems to work, the signals do not turn red in SignalTab). I will do the same on the ff_tx_* signals just to make sure and test again, but since I would be very surprised if that was the problem, I wanted to get a post out first. Any insight on how to get the MM interface responsive would be greatly appreciated :) EDIT: I checked again with basically all signals marked as "noprune". Additionally, I implemented an additional reset after the clocks have been stable for some time. Both actions did not change the behavior in any way.