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MAmin's avatar
MAmin
Icon for New Contributor rankNew Contributor
7 years ago
Solved

Native Phy Receiver not aligning properly

Hello I have a Native PHY set to receive a 20 bit pattern for alignment/synchronization of the receiver. I am sending the pattern however when the receiver receives it, it seems like it is aligning ...
  • CheepinC_altera's avatar
    CheepinC_altera
    7 years ago

    Hi,

    From the simulation​, seems like the PCS-core width is 32 bits which I believe you have enable byte SERDES in your transceiver. For your information, if you have byte SERDES enabled, after achieving the word alignment, you would need to perform the byte ordering to get the correct data. For example, from the simulation, seems like the MSByte and LSByte order is swapped.

    Just would like to check with you which device are you using? For V series devices, they have the byte ordering block supported.

    Thank you.

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

From the simulation​, seems like the PCS-core width is 32 bits which I believe you have enable byte SERDES in your transceiver. For your information, if you have byte SERDES enabled, after achieving the word alignment, you would need to perform the byte ordering to get the correct data. For example, from the simulation, seems like the MSByte and LSByte order is swapped.

Just would like to check with you which device are you using? For V series devices, they have the byte ordering block supported.

Thank you.