Forum Discussion
Altera_Forum
Honored Contributor
14 years agoI think we should see all the code to find out why it is trying to generate RAM blocks.
The mux you are trying to do will probably not work, as it will add a clock delay on the valid and ready signals in each direction. A transfer occurs when both signals are active at the same time, but in your case on every interface there will be two clock delays between those signals, and it will probably have unexpected results. You'll either have to add some buffering logic, or do a combinatorial multiplexer instead, with only the owner signal actually synchronized with the clock.