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5 months agoMulti-rate Ethernet valid signal behavior
I'm working with the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core on an Arria V device.
https://www.intel.com/content/www/us/en/docs/programmable/683171/current/introduction-to-the-protocol-specific.html#joc1445401896251
I fixed my IP to 2.5G and have a question about the gmii16b_rx_dv signal.
The datasheet explains that this signal marks which of the 2 bytes are valid:
Is it possible for one of the bits of gmii16b_rx_dv to be '0' in the middle of a packet ?
Or it can happen ONLY in the last byte ?
Hello,
Good day.
The lower byte (gmii16b_rxd[7:0]) contains the valid data.
Hope this answer your query.
Regards,
Pavee