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host
Occasional Contributor
Occasional ContributorMulti-rate Ethernet valid signal behavior
I'm working with the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core on an Arria V device. https://www.intel.com/content/www/us/en/docs/programmable/683171/current/introduction-to-the-protocol-specif...
Hello,
Good day.
The lower byte (gmii16b_rxd[7:0]) contains the valid data.
Hope this answer your query.
Regards,
Pavee
paveetirrasrie_Altera
Frequent Contributor
Frequent ContributorHello,
It can happen only in the last word of a packet.
In the middle of a packet, both bits of gmii16b_rx_dv should always be '1'.
Hope this answer your query.
Regards,
Pavee
hostThanks for the input.
When it does happen, which of the bytes will contain valid data [15:8] or [7:0] ?
