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Altera_Forum
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10 years ago

Multi-Port-Front-End DDR3 controller is too slow

Hi, I've using a Cyclone V SOC with 1Gbyte of DDR3 memory connected to the FPGA DDR3 pins - I've set the basic clock rate to 350MHz. I've got the NIOS CPU connected to this, and can verify that t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

There is really not enough information provided to help you.

As simple as that, you need to keep in mind that you are using a DDR3-RAM. If you only write 32 Bits words, there will be a lot of overhead because of the write/read Operation with BL8s in a DDR3. Also, there should be some logic for thr addressing. To many changes of the rows within one bank leads to bad performance. At least, you will never get the calculated maximum because you can not completly eliminate the latencies between activate, read, write, precharge and finally refresh cyclrs consumes time