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M_T's avatar
M_T
Icon for New Contributor rankNew Contributor
9 months ago

mSGDMA Data Loss Between Descriptors (Streaming to Memory-Mapped)

We're experiencing consistent data loss when using Altera's mSGDMA IP on an Arria 10 device for streaming data from the FPGA fabric to DDR memory (accessible by the HPS). Issue Description Data is...
Memory
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
7 months ago

Hi


Sorry for the late response.

I am Jingyang and will be helping out on this issue.


When you mention the interrupt is not triggerd. Could you check the Transfer Complete IRQ Enable is set in the descriptor?


Could you also check if the reset signal is being triggered after the first transfer?


Regards

Jingyang, Teh