mSGDMA Data Loss Between Descriptors (Streaming to Memory-Mapped)

Thank you for your response.

We have successfully resolved the data loss issue by ensuring the FPGA properly processes the READY signal.

We still have identified several critical issues in our FPGA implementation:

1. Interrupts are not triggered until all descriptors in the FIFO queue have been completely processed.
2. Even when implementing polling for responses, they remain unavailable until all FIFO descriptors are fully consumed.
3. When reading the responses, the length is zero, although the data is correctly transferred to the DDR memory.
4. Our development is within a Linux environment, requiring compatible software solutions.
5. The current Altera driver lacks proper user-space application interfacing capabilities. (Reference: https://github.com/altera-opensource/linux-socfpga/blob/socfpga-6.1.55-lts/drivers/dma/altera-msgdma.c)
6. When attempting to populate the descriptor FIFO using timer-based methods, we observe periodic system halts lasting tens of milliseconds.
7. As a workaround, we're currently processing single descriptors sequentially, which provides acceptable but suboptimal data throughput rates.
8. When trying to use F2SDRAM instead of F2H bus, the mSGDMA IP becomes stuck after the first transfer with the "Resetting" bit enabled in the Status register.

I would appreciate your expertise in addressing any of these challenges to improve our system performance.