Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThere is a reference design from altera (click) (https://www.altera.com/products/reference-designs/all-reference-designs/broadcast/ref-video.html)
Its application note can also be found here (click) (https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0ahukewi12qqg6ltrahxhqxokhz1rbw0qfggfmae&url=http%3a%2f%2fnotes-application.abcelectronique.com%2f038%2f38-21295.pdf&usg=afqjcngyplvkngmddttbcp8n6miujizjgw&sig2=wjakqccaz58f4ls9lfiyfw&bvm=bv.142059868,d.d2s&cad=rja) This reference design is too large (due to Nios) and lacks jitter control. If you want to design from scratch, it is not difficult. You should be well informed about MPEG-TS, RTP, UDP, and Gigabit Ethernet interface. You need a DDR controller and DDR memory if you want low jitter output, otherwise you can do it using FIFOs inside FPGA.