modified CAM

I've implemented a CAM/RAM combination in my design.

both CAM and RAM uses shared bus for their writing values and input (this is more common).

I want to use separated input & writing bus for both.I want an implementation with independent bus for each input data and writing data.

is it possible to modifying Altera's CAM?

if not is there a free VHDL/Verilog/... code available?