Forum Discussion
Altera_Forum
Honored Contributor
10 years agothx for answering
yes whatever input is the output is the same k28.5+ after k28.5- I havn't change version yet ! I do some other test , I try to change the ALTGX mode to strarixiv of no use I try to change the clk frequency of no use I try to use the modelsim "create wave" to generate the clk signal instead of the vhdl then the simulation can't work with "Fatal error in Process line__168 at K:/altera/15.0/quartus/eda/sim_lib/stratixiv_hssi_atoms.vhd line 172 " but what matters me most is when I download my design to the cyloneiv , it works , I can't believe it , that's good but that's not what I want! maybe I should change my modelsim version sinx