Modelsim 10.1 PE syntax error for "tse_10_100_1000_mac" IP core

From your post I could understand that you were trying to simulate TSE's test bench. But I have written design in VHDL and TSE Ip core design files are in verilog, which i compiled successfully except

altera_tse_top_gen_host.v (syntax error in this file- Encrypted file, Size : 62 Kb)

I am sharing my batch_run.bat , hoping you will get better clarity on the issue,

vlib work

vlib design

vmap work design

vcom -work design -f lib.dgn

vcom -work work -f lib.dgn

vlog -work work ../../design/altera_tse_reset_synchronizer.v

vlog -work work ../../design/altera_tse_top_gen_host.v

vlog -work work ../../design/altera_tse_mac.v

vcom -2008 -work work -f rtl.dgn

vcom -2008 -work work -f tb.dgn

vcom -2008 -work work ../tests/IF_FPGA_TS.vhd

vsim work.IF_FPGA_TB -l IF_FPGA_TEST.log -do msim.do -c -quiet -t 1ps

move IF_FPGA_TEST.log ../logs/IF_FPGA_TEST.log

move vsim.wlf ../waves/IF_FPGA_TEST.wlf

After running this script compiler is reporting the error.

** Error : ../../design/ altera_tse_top_gen_host.v (1) : Syntax error, unexpected non-printable character 0x8b

** Error : ../../design/ altera_tse_top_gen_host.v (1) :Syntax error, unexpected $undefined , expecting class

I have directly copied TSE's design files from quartus TSE directory to my design folder.