Forum Discussion
Jacky_chang
New Contributor
New ContributorMemory Interface : Arria_10 NIOS II + Address span extender + EMIF (x72 arria 10 GX DDR4 HILO)
NIOS II has a limit of 32bit data length, I need to turn on Cache and use EMIF, the bridge is Address span extender, How to define IP parameters for the address span extender between NIOS II and EMI...
tehjingy_Altera
Regular Contributor
Regular ContributorHi
Could not find any example design that you are looking at.
However I managed to gather some related document on configuring the Address Span extender in the link below:
https://community.intel.com/t5/FPGA-Wiki/Address-span-extender-example/ta-p/735149
https://www.intel.com/content/www/us/en/docs/programmable/683609/24-2/address-span-extender.html
Regards
Jingyang, Teh
