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New Contributor

2 years ago

Memory Interface : Arria_10 NIOS II + Address span extender + EMIF (x72 arria 10 GX DDR4 HILO)

NIOS II has a limit of 32bit data length, I need to turn on Cache and use EMIF, the bridge is Address span extender, How to define IP parameters for the address span extender between NIOS II and EMI...

Memory

tehjingy_Altera

Regular Contributor

2 years ago

Could not find any example design that you are looking at.

However I managed to gather some related document on configuring the Address Span extender in the link below:

https://community.intel.com/t5/FPGA-Wiki/Address-span-extender-example/ta-p/735149

https://www.intel.com/content/www/us/en/docs/programmable/683609/24-2/address-span-extender.html

Regards

Jingyang, Teh

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Memory Interface : Arria_10 NIOS II + Address span extender + EMIF (x72 arria 10 GX DDR4 HILO)

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