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WKett's avatar
WKett
Icon for New Contributor rankNew Contributor
6 years ago

Max10 Soft LVDS bit slip shouldn't be needed for odd serialization factors. How to shift bits with external pll mode using nothing but compile time phase adjustments?

Serialized bit phase alignment is deterministic for odd LVDS serialization factors as used by Channel Link interfaces.. In gate level simulation using Modelsim, I get properly phase aligned bits out...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Sure ..If you can kindly let me know input from FAE.

By the way , would it possibe to share only the tb on bit slip. I think it will save my time and i can check with just IP instantiation. It will help me to deep dive on your case.

Thank you ,

Regards,

Sree