Max10 Soft LVDS bit slip shouldn't be needed for odd serialization factors. How to shift bits with external pll mode using nothing but compile time phase adjustments?

One more actual question regarding the Soft LVDS Receiver IP... If arbitrary bit-slip values can be set within the deserialzer pipeline, why can users not set the bit-slip counter's reset value directly within the megafunction wizard? This would allow the reciever to be configured with a power-up defined word boundary alignment and extra useless code would not be necessary just for creating a prescribed number of pulses when using non-clock edge aligned word boundaries. A simple diagram/example showing bit alignment vs bit slip value anywhere in the LVDS users guides would have saved me several days of attempting to understand the Soft LVDS IP behavior. Please improve the documentation.