Max10 on chip flash ip core issue

this is what i'm see in the signaltap.

the flash is configured parallel and im using the 10M50DAF484 device (currently using the altera eval board).

my design is a qsys design, avmm pipeline bridge which is the master of the onchip flash (data and csr), dual boot and sysid slaves. the bridge is exported outside of the qsys design to my custom controller which translates uart commands to the avalon bus.

anyway i see that when i want to write data to the flash instead of sampling the waitrequest port for writing the next data, i need to wait in the host until writing the next data. why do you think the waitrequest signal dont acts as it supposed to be? as i understood from the ug_m10_ufm document, the waitrequest should be asserted for maximum 0.5 msec.

im working with quartus 15.1.0, maybe the ip is not last updated? if so, how do i update the ip?