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SOtsr's avatar
SOtsr
Icon for New Contributor rankNew Contributor
7 years ago

Max10 on chip flash ip core issue

I try to write data to the internal flash, noticed that somehow the waitrequest signal is asserted for one clock cycle only. The clock is 25mhz. I noticed it through the signaltap.. ​ Any idea?​
ShafiqY_Intel's avatar
ShafiqY_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi,

Typically, waitrequest signal assert when the On-Chip Flash IP is busy during read or write operation. However, for your case I’m not really sure why waitrequest only assert for one clock cycle. Could you please attach your signal screenshot here?

Do you choose parallel or serial option for Data Interface in On-Chip Flash IP parameter?

And one more thing, which MAX 10 family device you used for your design? (10M02 or 10M50 or ?)

Looking forward for your reply.

Thanks.😉