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Altera_Forum's avatar
Altera_Forum
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8 years ago

MAX10 ADC Core Channel Sequence Issue

Hi All, I am having a small issue with the ADC Core-only IP. I have two channels enabled (11 and 12) and a controller that sequences between them: Once 11 is converted, it starts 12, then 11,...
Altera_Forum's avatar
Altera_Forum
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8 years ago

I don't see how the t2 timing would be the culprit.

The IP that controls the ADC core is quite simple: It sets the command_valid signal high, and increments the command_channel after command_ready goes high. The other signals I am looking at with the signal tap.

I just did another test where I issued commands in the following sequence:

11, 11, 12, 12

and got the data in this sequence:

12, 11, 11, 12

So that does support the notion of latency, but based on the ADC timing diagram, my design _should_ account for that.

Thank you for the response.