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DR123's avatar
DR123
Icon for New Contributor rankNew Contributor
6 years ago

MAX 10 EMIF DDR3 velocity transfer issue

Hi, I'm working on a DECA development board and I'm trying to transfer data from a FIFO to the on-board DDR3 through a Scatter Gather DMA and an EMIF controller for the DDR. The data are correctly t...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

I will suggest you come out with details description, eg, screenshot of the signaltap and re-post as a new thread in embedded field. Apparently, this is not the DDR3 IP issue because you mentioned the avl_ready signal works.