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DR123's avatar
DR123
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6 years ago

MAX 10 EMIF DDR3 velocity transfer issue

Hi, I'm working on a DECA development board and I'm trying to transfer data from a FIFO to the on-board DDR3 through a Scatter Gather DMA and an EMIF controller for the DDR. The data are correctly t...
DR123's avatar
DR123
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6 years ago

Hi,

thank you for the answer. Yes, the ready signal is the "avl_ready" of the DDR3 controller. The waitrequest is an input for the DMA that is only connected with the DDR3 controller. I supposed that the waitrequest was exactly the avl_ready (actually the NOT of avl_ready), but it seems that they are different. Is it possible that the Platform Designer inserts an adapter that handles this signal?