Occasional Contributor
Super ContributorSanity check question: is your control register address at 100 because of byte addressing?
I see nothing in your code for checking waitrequest. You have the input signal, but you haven't coded for it. You mention a "busy signal". Is that supposed to be waitrequest? Edit: no, you're talking about the busy states of the IP. Nevermind.
Waitrequest could certainly be your problem. Have you set up Signal Tap yet to test while running in hardware?
Occasional Contributormy address is at 100 because that's the only way I got a response. Although the manual states that status and control register are on address 0 and 1, the platform designer put the address range for the csr interface on 0x0 to 0x7. But when I actually used '000' and '001' as addresses, nothing happened. In the spirit of "why not try this" I changed the bit to set the address and "100" worked. No idea why that works.
The waitrequest signal is only there because an avalon MM master needs it, but the CSR interface doesn't have a waitrequest signal. So I don't think I have to look at it, for the CSR interface. I indeed meant the busy state of the IP.
I have not set up Signal Tap yet. I'll look into it and try to find a manual. If you have a correct manual to set this up, please share
I did investigate some signals through available LEDs and those seemed alright. But hey, something is clearly wrong, so I'll investigate the signal tap.
In any case, the weird thing is the "erase successful" bit is clearly set in simulation and in hardware (again, seen through LED), yet nothing seems to be erased...
Super ContributorThe address needs to be 100 because hosts (previously referred to as masters) use byte addressing. As such, you have to increase the address by 4 to get to subsequent 32-bit registers in the agent (previously referred to as slaves).
Just because you don't see waitrequest on the agent side, in a Platform Designer system, waitrequest is required on the host side. The interconnect controls it if it is not present from the agent. address and waitrequest are the only required Avalon signals for a host. All the others are optional depending on the types of transfers you want to support. Without waitrequest checking, you have no guarantee that that "erase successful" bit read is valid or not.
The Signal Tap online trainings were just updated. They'll link you to the debug tools user guide. Start here:
