Honored ContributorHi,
is there a way to convert a LVDS video signal to Avalon Streaming protocol? This conversion is necessary to use the Video and Image Processing (VIP) Suite. best regards occino
Honored Contributorif the video on the LVDS bus follows a video standard supported by the Clocked Video Input block, you can connect them to get into the "Video ST" domain
if not you'll need to write RTL to convert between the twoHonored Contributorthank you for the quick reply!
i have 4 lvds pairs and the related clock pair. evey lane has 7 bits therfore i have 28 bits which are deserialized by the ALTLVDS_RX. i will give a try to the Clocked Video Input block and report about success or problemsHonored Contributori don't think the CVI will work, you'll have to build your own component
it shouldn't be too difficultHonored ContributorI'm using the JEIDA protocol. i guess i have to pick all single color bits, the h/v-sync bits and the clock to create a conversation modul for using the CVI. should i implement this modul in vhdl or is there an easier way? have you got a simple example code for getting started?
thanks a lot! Jeida protocol: i41.tinypic.com/33le2vt.jpg (sorry, i cant post this image correctly because i've only 3 posts :oops:)Honored Contributorbefore i can start i have an other small question.
the ALTLVDS_RX has 28 outout signals but i can't assign them to R,G,B and the sync signal. is there a way to figure out how the deserializer assign the bits?Honored Contributori'm not sure i would bother generating the data for CVI, you might as well go straight for Avalon ST. essentially, you are making a custom CVI
Honored Contributori'm progressed with my problem, but for my purpose i have to split the project into smaller testable units.
i will continue this thread as soon as i have a solution
