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We were going to add pipeline stages eventually
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Don't wait until the end, add them as you design the logic. If you are using DSP blocks, then look at their operating modes in the handbook for the device you are using, and instantiate or infer a calculation that maps to a DSP block exactly, including the pipeline registers (output registers).
You stated that you plan on operating at 125MHz. This should be easily achieved using DSP blocks and pipeline registers in Cyclone/Arria/Stratix devices.
You do not have to use LPM/MF components for DSP calculations. The Quartus handbook (and templates) and the Stratix Cookbook show various techniques for inferring logic. If you place-and-route and look at the implemented logic, you can check if your code has been inferred correctly.
Cheers,
Dave
Honored Contributor
