LPDDR3 Simulation using example design
I'm having some issues with the LPDDR3 IP in my project. See attached lpddr3.ip file in the ZIP
As a sanity test, I create the Intel LPDDR3 example design via Platform Designer, using the attached IP file without change.
(Hard Controller/PHY, LPDDR3-1600 4Gb (128Mbx32) from the presets, 800MHz mem clock with 200Mhz ref, autopch control ON (or OFF), Verilog, no board)
I then simulate with Modelsim-AE 2021.1 version. I get some very strange results with all kinds of warnings and complaints. The load itself has a number of warnings involving items in the protected portion of the design. Running the test for 100uS gives the attached transcript.
Note: I have also run this with the abbreviated calibration option and these messages persist after calibration "succeeds." Note that for the most part the control and data wires to the memory are not moving.
(Win10Pro 21H1 19043, QPP 21.2, AMD Ryzen 7 5800x)
Never mind. I rebuilt the project from source and paid careful attention to sequences, and it works fine now. Apparently there was a build problem somewhere along the line and things were unhappy.