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Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

LPDDR2 IP woes

I am using the Quartus Lite application from 17.1 to 22.1, all varieties have been tested. In essence I am porting a design that was tested on a: Terasic Technologies Cyclone V GX Starter Kit ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Mike,


Thanks for the update.

I just want to clarify your problem.

You can use the EMIF Toolkit if you are using Cyclone V GX Starter Kit but you can't use if you are using your own custom board?


Can you provide the error that you are facing when linking the project to device?


In the LPDDR2 IP, are you already configure the Board Settings according to your own custom board?


Do you see any timing violation in the design?


Here is the link for LPDDR2 example design that you can refer to. There also a video that provides some explanation about the example design. https://community.intel.com/t5/FPGA-Wiki/TerASIC-LPDDR2-Example/ta-p/735535


Thanks,

Adzim


Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

I see, so what you are saying is that I cannot use the LPDDR2 SDRAM Controller IP?

I'm not getting as far as a working design. The issue is over using Intel IP Megafunction and trying to get the External Memory Interface Toolkit to work without crashing Quartus.

Yes, I have checked and double checked the pins are set correctly in the qsf file, device etc. The error is in my first post?